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Shangqing Zhao

Richard Veras
Office: DEH 331



PhD, Electrical and Computer Engineering, Carnegie Mellon University

MS, Electrical and Computer Engineering, Carnegie Mellon University

BS, Mathematics, The University of Texas at Austin

BS, Computer Science, The University of Texas at Austin


Assistant Professor, University of Oklahoma

Research Scientist, Louisiana State University

Postdoctoral Research Associate, Carnegie Mellon University


Research in all facets of High Performance Computing (HPC) including code synthesis for performance, parallel algorithm design; crafting  libraries for computational linear algebra, signal processing, graph analytics; studying relationship between data and computer architecture, parallel hardware, accelerators, reconfigurable logic and distributed systems.


Dr. Richard M. Veras is an Assistant Professor in the School of Computer Science at the University of Oklahoma. He received a BS in Computer Science and a BS in Mathematics at the University of Texas. He received his MS and PhD in Electrical and Computer Engineering at Carnegie Mellon University. His research focuses on the underlying science of High Performance Computing (HPC), turning that knowledge into systematic processes for synthesizing efficient software and hardware, and automating the processes into usable tools.


S. G. Krishna, A. Narasimhan, S. Radhakrishnan, R. Veras, On Large-Scale Matrix-Matrix Multiplication on Compressed Structures, IEEE Workshop on Big Data Reduction. 2021.

R. Li, A. Rajam, R. Veras, T. M. Low, F. Rastello, P. Sadayappan. Analytical Cache Modeling and Tilesize Optimization for Tensor Contractions. Supercomputing (SC). 2019.

F. Franchetti, T. M. Low, D. Popovici, R. Veras, D. Spampinato, J. Johnson, M. Puschel, J. Hoe, J. Moura, SPIRAL: Extreme Performance Portability. Proceedings of the IEEE. 2019.

R. Veras, T. M. Low, T. Smith, F. Franchetti, R. van de Geijn, Automating the Last-Mile for High Performance Dense Linear Algebra. ArXiv. 2016.

R. Veras, F. Franchetti, A Scale-Free Structure for Real-World Graphs. IEEE High Performance Extreme Computing Conference (HPEC). 2017.

R. Veras, T. M. Low, F. Franchetti, A Scale-Free Structure for Power-Law Graphs. IEEE High Performance Extreme Computing Conference (HPEC). 2016.

R. Veras, D. Popovici, T. M. Low, F. Franchetti, Compilers, Hands Off My Hands On Code. Workshop on Programming Models for SIMD/Vector Processing (WPMVP). 2016.

R. Veras, F. Franchetti, Capturing the Expert: Generating Fast Matrix-Multiply Kernels with Spiral. International Workshop on Automatic Performance Tuning (iWAPT). 2014.

T. Henretty, R. Veras, F. Franchetti, L. N. Pouchet, J. Ramanujam, P. Sadayappan, A stencil compiler for short-vector SIMD architectures. International Conference on Supercomputing (ICS). 2013.

M. Kong, R. Veras, K. Stock, F. Franchetti, L. N. Pouchet, P. Sadayappan, When polyhedral transformations meet SIMD code generation. ACM Programming Language Design and Implementation (PLDI). 2013.

J. Liu, B. Jaiyen, R. Veras, O. Mutlu, RAIDR: Retention-Aware Intelligent DRAM Refresh. International Symposium on Computer Architecture (ISCA). 2012.

R. Veras, J. Monette, R. van de Geijn, Quintana-Orti, FLAMES2S: From Abstraction to High Performance. The University of Texas at Austin, Department of Computer Sciences. Technical Report TR-08-49. 2008.